C8051F300_08 Datasheet, PDF (4/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 73
8.3.5. Interrupt Register Descriptions................................................................. 75
8.4. Power Management Modes .............................................................................. 80
8.4.1. Idle Mode.................................................................................................. 80
8.4.2. Stop Mode ................................................................................................ 81
9. Reset Sources......................................................................................................... 83
9.1. Power-On Reset ............................................................................................... 84
9.2. Power-Fail Reset/VDD Monitor......................................................................... 84
9.3. External Reset .................................................................................................. 85
9.4. Missing Clock Detector Reset........................................................................... 85
9.5. Comparator0 Reset........................................................................................... 85
9.6. PCA Watchdog Timer Reset............................................................................. 85
9.7. Flash Error Reset.............................................................................................. 86
9.8. Software Reset ................................................................................................. 86
10. Flash Memory ......................................................................................................... 89
10.1.Programming The Flash Memory ..................................................................... 89
10.1.1.Flash Lock and Key Functions ................................................................. 89
10.1.2.Flash Erase Procedure ............................................................................ 89
10.1.3.Flash Write Procedure ............................................................................. 90
10.2.Non-Volatile Data Storage................................................................................ 90
10.3.Security Options ............................................................................................... 90
10.4.Flash Write and Erase Guidelines .................................................................... 94
10.4.1.V_DD Maintenance and the V_DD monitor ................................................... 94
10.4.2.PSWE Maintenance ................................................................................. 94
10.4.3.System Clock ........................................................................................... 95
11. Oscillators ............................................................................................................... 97
11.1.Programmable Internal Oscillator ..................................................................... 97
11.2.External Oscillator Drive Circuit........................................................................ 99
11.3.System Clock Selection.................................................................................... 99
11.4.External Crystal Example ............................................................................... 101
11.5.External RC Example ..................................................................................... 102
11.6.External Capacitor Example ........................................................................... 102
12. Port Input/Output.................................................................................................. 103
12.1.Priority Crossbar Decoder .............................................................................. 104
12.2.Port I/O Initialization ....................................................................................... 106
12.3.General Purpose Port I/O ............................................................................... 108
13. SMBus ................................................................................................................... 111
13.1.Supporting Documents ................................................................................... 112
13.2.SMBus Configuration...................................................................................... 112
13.3.SMBus Operation ........................................................................................... 112
13.3.1.Arbitration............................................................................................... 113
13.3.2.Clock Low Extension.............................................................................. 114
13.3.3.SCL Low Timeout................................................................................... 114
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 114
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Rev. 2.9