C8051F300_08 Datasheet, PDF (53/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 72). The CP0FIF flag
is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the
Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The output
state of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by
setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W
CP0EN
Bit7
R
CP0OUT
Bit6
R/W
CP0RIF
Bit5
R/W
CP0FIF
Bit4
R/W
R/W
R/W
R/W
Reset Value
CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit3
Bit2
Bit1
Bit0 SFR Address:
(bit addressable) 0xF8
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2:
Bits1–0:
CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
CP0RIF: Comparator0 Rising-Edge Interrupt Flag.
0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Rising Edge Interrupt has occurred.
CP0FIF: Comparator0 Falling-Edge Interrupt Flag.
0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 2.9
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