C8051F300_08 Datasheet, PDF (60/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
ANL direct, A
AND A to direct byte
2
ANL direct, #data
AND immediate to direct byte
3
ORL A, Rn
OR Register to A
1
ORL A, direct
OR direct byte to A
2
ORL A, @Ri
OR indirect RAM to A
1
ORL A, #data
OR immediate to A
2
ORL direct, A
OR A to direct byte
2
ORL direct, #data
OR immediate to direct byte
3
XRL A, Rn
Exclusive-OR Register to A
1
XRL A, direct
Exclusive-OR direct byte to A
2
XRL A, @Ri
Exclusive-OR indirect RAM to A
1
XRL A, #data
Exclusive-OR immediate to A
2
XRL direct, A
Exclusive-OR A to direct byte
2
XRL direct, #data
Exclusive-OR immediate to direct byte
3
CLR A
Clear A
1
CPL A
Complement A
1
RL A
Rotate A left
1
RLC A
Rotate A left through Carry
1
RR A
Rotate A right
1
RRC A
Rotate A right through Carry
1
SWAP A
Swap nibbles of A
1
Data Transfer
MOV A, Rn
Move Register to A
1
MOV A, direct
Move direct byte to A
2
MOV A, @Ri
Move indirect RAM to A
1
MOV A, #data
Move immediate to A
2
MOV Rn, A
Move A to Register
1
MOV Rn, direct
Move direct byte to Register
2
MOV Rn, #data
Move immediate to Register
2
MOV direct, A
Move A to direct byte
2
MOV direct, Rn
Move Register to direct byte
2
MOV direct, direct
Move direct byte to direct byte
3
MOV direct, @Ri
Move indirect RAM to direct byte
2
MOV direct, #data
Move immediate to direct byte
3
MOV @Ri, A
Move A to indirect RAM
1
MOV @Ri, direct
Move direct byte to indirect RAM
2
MOV @Ri, #data
Move immediate to indirect RAM
2
MOV DPTR, #data16
Load DPTR with 16-bit constant
3
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
Clock
Cycles
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
1
1
1
1
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
60
Rev. 2.9