C8051F300_08 Datasheet, PDF (109/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
SFR Definition 12.4. P0: Port0 Register
R/W
P0.7
Bit7
R/W
P0.6
Bit6
R/W
P0.5
Bit5
R/W
P0.4
Bit4
R/W
P0.3
Bit3
R/W
P0.2
Bit2
R/W
R/W
Reset Value
P0.1
P0.0 11111111
Bit1
Bit0 SFR Address:
(bit addressable) 0x80
Bits7–0:
P0.[7:0]
Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers
0: Logic Low Output.
1: Logic High Output (open-drain if corresponding P0MDOUT.n bit = 0)
Read - Always reads ‘1’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 12.5. P0MDIN: Port0 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xF1
Bits7–0:
Input Configuration Bits for P0.7-P0.0 (respectively)
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is configured as a digital input.
Rev. 2.9
109