C8051F300_08 Datasheet, PDF (163/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
16.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-bit PWM mode. In this mode, the 16-bit capture/compare mod-
ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is set to ‘1’; when the counter overflows, CEXn is set to ‘0’. To
output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts.
16-bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register.
For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchro-
nize the capture/compare register writes. The duty cycle for 16-bit PWM Mode is given by Equation 16.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
DutyCycle = ^---6---5---5---3---6----–-----^P----^C----^A----0----^C----^P----ⁿ----^
65536
Equation 16.3. 16-Bit PWM Duty Cycle
Using Equation 16.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
1 00x0 x
PCA0CPHn PCA0CPLn
Enable
16-bit Comparator
match _S SET _Q
CEXn _Crossbar
PCA Timebase
PCA0H
PCA0L
Overflow
RQ
CLR
Figure 16.9. PCA 16-Bit PWM Mode
Port I/O
Rev. 2.9
163