C8051F300_08 Datasheet, PDF (74/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Table 8.4. Interrupt Summary
Interrupt Source
Interrupt Priority
Vector Order Pending Flag
Enable
Flag
Priority
Control
Reset
0x0000 Top None
N/A N/A _{Always Always}
Enabled Highest
External Interrupt 0 (/INT0) 0x0003
0 IE0 (TCON.1)
Y Y _{EX0 (IE.0) PX0 (IP.0)}
Timer 0 Overflow
0x000B
1 TF0 (TCON.5) ^{Y Y} ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/INT1) 0x0013
2 IE1 (TCON.3)
Y Y _{EX1 (IE.2) PX1 (IP.2)}
Timer 1 Overflow
0x001B
3 TF1 (TCON.7) ^{Y Y} ET1 (IE.3) PT1 (IP.3)
UART0
Timer 2 Overflow
0x0023
0x002B
4 RI0 (SCON0.0) ^{Y N} ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
5 TF2H
Y N _{ET2 (IE.5) PT2 (IP.5)}
(TMR2CN.7)
SMBus Interface
0x0033
ADC0 Window Compare 0x003B
ADC0 Conversion Com-
plete
Programmable Counter
Array
0x0043
0x004B
Comparator0 Falling Edge 0x0053
Comparator0 Rising Edge 0x005B
TF2L
(TMR2CN.6)
6 SI (SMB0CN.0) ^{Y N} ESMB0 PSMB0
(EIE1.0) (EIP1.0)
7 AD0WINT
Y N _{EWADC0 PWADC0}
(ADC0CN.3)
(EIE1.1) (EIP1.1)
8 AD0INT
Y N _{EADC0C PADC0C}
(ADC0CN.5)
(EIE1.2) (EIP1.2)
9 CF (PCA0CN.7) ^{Y N} EPCA0 PPCA0
CCFn
(EIE1.3) (EIP1.3)
(PCA0CN.n)
10 CP0FIF
N N _{ECP0F PCP0F}
(CPT0CN.4)
(EIE1.4) (EIP1.4)
11 CP0RIF
N N _{ECP0R PCP0R}
(CPT0CN.5)
(EIE1.5) (EIP1.5)
74
Rev. 2.9