C8051F300_08 Datasheet, PDF (8/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
10. Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 91
11. Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 97
Figure 11.2. 32.768 kHz External Crystal Example................................................ 101
12. Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram ..................................................... 103
Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105
13. SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 111
Figure 13.2. Typical SMBus Configuration ............................................................. 112
Figure 13.3. SMBus Transaction ............................................................................ 113
Figure 13.4. Typical SMBus SCL Generation......................................................... 117
Figure 13.5. Typical Master Transmitter Sequence................................................ 123
Figure 13.6. Typical Master Receiver Sequence.................................................... 124
Figure 13.7. Typical Slave Receiver Sequence...................................................... 125
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126
14. UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 131
Figure 14.2. UART0 Baud Rate Logic .................................................................... 132
Figure 14.3. UART Interconnect Diagram .............................................................. 133
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135
15. Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152
16. Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 155
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157
Figure 16.4. PCA Capture Mode Diagram.............................................................. 158
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 159
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160
Figure 16.7. PCA Frequency Output Mode ............................................................ 161
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164
17. C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 175
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Rev. 2.9