C8051F300_08 Datasheet, PDF (29/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Figure 4.2. QFN-11 Package Drawing
Table 4.2. QFN-11 Package Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
0.80
0.90
1.00
E
3.00 BSC.
A1
0.03
0.07
0.11
E2
2.20
2.25
2.30
A3
0.25 REF
L
.45
.55
.65
b
0.18
0.25
0.30
aaa
--
--
0.15
D
3.00 BSC.
bbb
--
--
0.15
D2
1.30
1.35
1.40
ddd
--
--
0.05
e
0.50 BSC.
eee
--
--
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-243, variation VEED except for custom features D2, E2, and L
which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Rev. 2.9
29