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C8051F300_08 Datasheet, PDF (85/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
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C8051F300/1/2/3/4/5
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic â1â to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read â1â, signifying the MCD as the reset source; otherwise,
this bit reads â0â. Writing a â1â to the MCDRSF bit enables the Missing Clock Detector; writing a â0â disables
it. The state of the RST pin is unaffected by this reset.
9.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a â1â to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0â), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read â1â signifying
Comparator0 as the reset source; otherwise, this bit reads â0â. The state of the RST pin is unaffected by
this reset.
9.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section â16.3. Watchdog Timer Modeâ on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to â1â. The state of the RST pin is unaffected by this reset.
Rev. 2.9
85
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