C8051F300_08 Datasheet, PDF (160/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
16.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
x 00
0x
PCA0CPLn PCA0CPHn
PCA Interrupt
PCA0CN
CC
CCC
FR
CCC
FFF
210
Enable
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Match
Toggle
0
1
TOGn
0 _{CEXn Crossbar}
1
Figure 16.6. PCA High Speed Output Mode Diagram
Port I/O
160
Rev. 2.9