C8051F300_08 Datasheet, PDF (127/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
13.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform with the SMBus specification. Highlighted responses are allowed but do not conform
to the SMBus specification.
Values Read
Table 13.4. SMBus Status Decoding
Current SMbus State
Typical Response Options
Values
Written
1110 0 0 X A master START was generated. Load slave address + R/W
into SMB0DAT.
00X
1100 0 0 0 A master data or address byte Set STA to restart transfer.
was transmitted; NACK received. _{Abort transfer.}
10X
01X
0 0 1 A master data or address byte Load next data byte into
was transmitted; ACK received. SMB0DAT
00X
End transfer with STOP
01X
End transfer with STOP and 1 1 X
start another transfer.
Send repeated START
10X
Switch to Master Receiver 0 0 X
Mode (clear SI without writ-
ing new data to SMB0DAT).
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