C8051F300_08 Datasheet, PDF (68/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Register
Table 8.3. Special Function Registers* (Continued)
Address
Description
TH1
0x8D
Timer/Counter 1 High
TL0
0x8A
Timer/Counter 0 Low
TL1
TMOD
0x8B
0x89
Timer/Counter 1 Low
Timer/Counter Mode
TMR2RLH
0xCB
Timer/Counter 2 Reload High
TMR2RLL
TMR2H
0xCA
0xCD
Timer/Counter 2 Reload Low
Timer/Counter 2 High
TMR2L
0xCC
Timer/Counter 2 Low
XBR0
XBR1
0xE1
0xE2
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
XBR2
0xE3
Port I/O Crossbar Control 2
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
Reserved
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Page
No.
150
150
150
148
154
154
154
154
107
107
108
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
68
Rev. 2.9