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C8051F300_08 Datasheet, PDF (26/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
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C8051F300/1/2/3/4/5
Table 3.1. Global Electrical Characteristics (Continued)
â40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
IDD Supply Sensitivity (Note 3) F = 25 MHz
F = 1 MHz
â 47 â
%/V
â 59 â
%/V
IDD Frequency Sensitivity
(Note 3, Note 5)
VDD = 3.0 V, F <= 1 MHz, T = 25 °C
VDD = 3.0 V, F > 1 MHz, T = 25 °C
â 0.27 â mA/MHz
â 0.10 â mA/MHz
VDD = 3.6 V, F <= 1 MHz, T = 25 °C
â 0.35 â mA/MHz
VDD = 3.6 V, F > 1 MHz, T = 25 °C
â 0.12 â mA/MHz
Digital Supply Currentï
(Stop Mode, shutdown)
Oscillator not running,
VDD Monitor Disabled
â < 0.1 â
µA
Notes:
1. Given in Table 9.2 on page 86.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data; Not production tested.
4. Normal IDD can be estimated for frequencies <= 15 MHz by simply multiplying the frequency of interest by
the frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. ï
For example: VDD = 3.0 V; F = 20 MHz, IDD = 6.6 mA â (25 MHz â 20 MHz) x 0.16 mA/MHz = 5.8 mA.
5. Idle IDD can be estimated for frequencies <= 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the
estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. ï
For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 3.3 mA â (25 MHz â 5 MHz) x 0.10 mA/MHz = 1.3 mA.
26
Rev. 2.9
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