C8051F300_08 Datasheet, PDF (176/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
DOCUMENT CHANGE LIST
Revision 2.3 to Revision 2.4
• Removed preliminary tag.
• Changed all references of MLP package to
QFN package.
• Pinout chapter: Figure 4.3: Changed title to
“Typical QFN-11 Solder Paste Mask.”
• ADC chapter: Added reference to minimum
tracking time in the Tracking Modes section.
• Comparators chapter: SFR Definition 7.3,
CPT0MD: Updated the register reset value and
the CP0 response time table.
• CIP51 chapter: Updated IDLE mode and rec-
ommendations.
• CIP51 chapter: Updated Interrupt behavior and
EA recommendations.
• CIP51 chapter: SFR Definition 8.4, PSW: Clari-
fied OV flag description.
• CIP51 chapter: SFR Definition 8.8, IP register:
Changed “default priority order” to “low priority”
for low priority descriptions.
• Reset Sources chapter: Clarified description of
VDD Ramp Time.
• Reset Sources chapter: Table 9.2, “Reset Elec-
trical Characteristics”: Added VDD Ramp Time
and changed “VDD POR Threshold” to “VDD
Monitor Threshold.”
• FLASH Memory chapter: Clarified descriptions
of FLASH security features.
• Oscillators chapter: Table 11.1 “Internal Oscil-
lator Electrical Characteristics”: Added Cali-
brated Internal Oscillator specification over a
smaller temperature range.
• Oscillators chapter: Clarified external crystal
initialization steps and added a specific
32.768 kHz crystal example.
• Oscillators chapter: Clarified external capacitor
example.
• SMBus chapter: Figure 14.5, SMB0CF regis-
ter: Added a description of the behavior of
Timer 3 in split mode if SMBTOE is set.
• Timers chapter: Changed references to “TL2”
and “TH2” to “TMR2L” and “TMR2H,” respec-
tively.
Revision 2.4 to Revision 2.5
• Fixed variables and applied formatting
changes.
Revision 2.5 to Revision 2.6
• Updated Table 1.1 Product Selection Guide to
include Lead-free information.
Revision 2.6 to Revision 2.7
• Removed non-RoHS compliant devices from
Table 1.1, “Product Selection Guide,” on
page 14.
• Added MIN and MAX specifications for ADC
Offset Error and ADC Full Scale Error to
Table 5.1, “ADC0 Electrical Characteristics,”
on page 47.
• Improved power supply specifications in
Table 3.1, “Global Electrical Characteristics,”
on page 25.
• Added Section “10.4. Flash Write and Erase
Guidelines” on page 94.
• Fixed minor typographical errors throughout.
Revision 2.7 to Revision 2.8
• Updated block diagram on page 1.
Revision 2.8 to Revision 2.9
• Updated QFN package drawings and notes.
• Added SOIC-14 package information.
• Added text to CPT0CN's SFR definition to indi-
cate that the SFR is bit addressable.
• Changed SMBus maximum transfer speed
from 1/10th system clock to 1/20th system
clock in SMBus section.
• Added information pertaining to Slave
Receiver and Slave Transmitter states in Table
13.4.
• Changed Table 5.1 and Figure 5.4 to indicate
that 11 SAR clocks are needed for a SAR con-
version to complete.
• Changed SCON0s SFR definition to show that
SCON0 bit 6 always resets to a value of 1.
176
Rev. 2.9