RX62T_15 Datasheet, PDF (97/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
Table 4.2
List of I/O Registers (Bit Order) (30 / 30)
Module
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
FLASH
FSTATR0
FRDY
ILGLERR
ERSERR
PRGERR
SUSRDY
—
ERSSPD
PRGSPD
FLASH
FSTATR1
FCUERR
—
—
FLOCKST
—
—
—
—
FLASH
FENTRYR
FEKEY[7:0]
FENTRYD
—
—
—
—
—
—
FENTRY0
FLASH
FPROTR
FPKEY[7:0]
—
—
—
—
—
—
—
FPROTCN
FLASH
FRESETR
FRKEY[7:0]
—
—
—
—
—
—
—
FRESET
FLASH
FCMDR
CMDR[7:0]
PCMDR[7:0]
FLASH
FCPSR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ESUSPMD
FLASH
DFLBCCNT
—
—
—
—
—
BCADR[7:0]
BCADR[7:0]
—
BCSIZE
FLASH
FPESTAT
—
—
—
—
—
—
—
—
PEERRST[7:0]
FLASH
DFLBCSTAT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BCST
FLASH
PCKAR
—
—
—
—
—
—
—
—
PCKA[7:0]
Note: • In this, the I/O port related registers (0008 C001h to 0008 C116h) indicate the bit configuration of the 112-pin LQFP version. As
the configuration of registers and bits differs depending on a package, see section 14, I/O Ports, for details in the User’s manual:
Hardware.
Note 1. This shows the bit configuration when ADDPR.DPSEL = 0 and ADDPR.DPPRC = 0 (The value has 10-bit accuracy and is
padded at the LSB end).
Note 2. This shows the bit configuration when ADCER.ADRFMT  0 (aligned to the LSB end) and ADCER.ADPRC[1:0]  00b. For
details, refer to section 28, 12-Bit A/D Converter (S12ADA) in the User’s manual: Hardware.
Note 3. This function is not supported by the product without the CAN function.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 97 of 134