RX62T_15 Datasheet, PDF (112/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
Table 5.11 Timing of On-Chip Peripheral Modules (3)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
RSPI
RSPCK clock cycle
RSPCK clock high pulse width
RSPCK clock low pulse width
RSPCK clock rise/fall time
Data input setup time
Data input hold time
SSL setup time
SSL hold time
Data output delay time
Master
Slave
Master
Slave
Master
Slave
Output
Input
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Symbol
t_SPcyc
t_SPCKWH
t_SPCKWL
t_SPCKR
t_SPCKF
t_SU
t_H
t_LEAD
t_LAG
t_OD
Min.
4
8
(t_Spcyc - t_SPCKR -
t_SPCKF) / 2-3
(t_Spcyc - t_SPCKR -
t_SPCKF) / 2
(t_Spcyc - t_SPCKR -
t_SPCKF) / 2-3
(t_Spcyc - t_SPCKR -
t_SPCKF) / 2
-
-
25
0
0
20+2t_Pcyc
1
4
1
4
-
-
Data output hold time
Master t_OH
Slave
Successive transmission delay time Master t_TD
MOSI, MISO rise/fall time
SSL rise/fall time
Slave access time
Slave output release time
Slave
Output
Input
Output
Input
t_DR
t_DF
t_SSLR
t_SSLF
t_SA
t_REL
0
0
t_SPcyc+2t_Pcyc
4t_Pcyc
-
-
-
-
-
-
Max.
4096
4096
-
Unit
t_Pcyc
Test
Conditions
Figure 5.11
ns
-
-
ns
-
5
1
-
-
-
-
8
-
8
-
20
3t_Pcyc
+40
-
-
8t_SPcyc
+2t_Pcyc
-
15
1
15
1
4
3
ns
s
ns
Figure 5.12 to
Figure 5.15
ns
t_SPcyc
t_Pcyc
t_SPcyc
t_Pcyc
ns
ns
ns
ns
s
ns
s
t_Pcyc
t_Pcyc
Figure 5.12 to
Figure 5.15
Figure 5.12 to
Figure 5.15
Note: • Note 1: t_Pcyc: PCLK cycle
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 112 of 134