RX62T_15 Datasheet, PDF (109/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
5.3.3
Timing of On-Chip Peripheral Modules
Table 5.9
Timing of On-Chip Peripheral Modules (1)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
SCI
Input clock cycle
Asynchronous
Clock synchronous
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle Asynchronous
Clock synchronous
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time (clock synchronous)
Receive data setup time (clock synchronous)
Receive data hold time (clock synchronous)
Symbol
t_Scyc
t_SCKW
t_SCKr
t_SCKf
t_Scyc
t_SCKW
t_SCKr
t_SCKf
t_TXD
t_RXS
t_RXH
Min.
4t_Pcyc
6t_Pcyc
0.4t_Pcyc
-
-
16t_Pcyc
6t_Pcyc
0.4t_Scyc
-
-
-
40
40
Typ.
-
-
0.6t_Scyc
20
20
-
-
0.6t_Scyc
20
20
40
-
-
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Figure 5.8
Figure 5.9
Note: • t_Pcyc: PCLK cycle
SCKn
(n = 0 to 2)
Figure 5.8
SCK Clock Input Timing
t_SCKW
t_SCKr
t_SCKf
t_Scyc
SCKn
TxDn
RxDn
t_TXD
t_RXS t_RXH
n = 0 to 2
Figure 5.9
SCI Input/Output Timing: Clock Synchronous Mode
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 109 of 134