RX62T_15 Datasheet, PDF (39/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
3. Address Space
3. Address Space
3.1 Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory maps.
Single-chip mode*¹
R5F562TAxxxx
0000 0000h
0000 4000h
0008 0000h
On-chip RAM
Reserved area*²
Peripheral I/O registers
0010 0000h
0010 8000h
007F 8000h
007F A000h
007F C000h
007F C500h
On-chip ROM
(data flash)
Reserved area*²
FCU-RAM*³
Reserved area*²
Peripheral I/O registers
Reserved area*²
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area*²
00FC 0000h
0100 0000h
On-chip ROM (program ROM)
(write only)
Single-chip mode*¹
R5F562T7xxxx
0000 0000h
0000 2000h
0008 0000h
On-chip RAM
Reserved area*²
Peripheral I/O registers
0010 0000h
0010 2000h
007F 8000h
007F A000h
007F C000h
007F C500h
On-chip ROM
(data flash)
Reserved area*²
FCU-RAM*³
Reserved area*²
Peripheral I/O registers
Reserved area*²
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area*²
00FE 0000h
0100 0000h
On-chip ROM (program ROM)
(write only)
Single-chip mode*¹
R5F562T6xxxx
0000 0000h
0000 2000h
0008 0000h
On-chip RAM
Reserved area*²
Peripheral I/O registers
0010 0000h
0010 2000h
007F 8000h
007F A000h
007F C000h
007F C500h
On-chip ROM
(data flash)
Reserved area*²
FCU-RAM*³
Reserved area*²
Peripheral I/O registers
Reserved area*²
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area*²
00FF 0000h
0100 0000h
On-chip ROM (program ROM)
(write only)
Reserved area*²
Reserved area*²
Reserved area*²
FEFF E000h
FF00 0000h
On-chip ROM (FCU firmware)*³
(read only)
Reserved area*²
FEFF E000h
FF00 0000h
On-chip ROM (FCU firmware)*³
(read only)
Reserved area*²
FEFF E000h
FF00 0000h
On-chip ROM (FCU firmware)*³
(read only)
Reserved area*²
FFFC 0000h _{On-chip ROM (program ROM)}
FFFF FFFFh
(read only)
FFFE 0000h _{On-chip ROM (program ROM)}
FFFF FFFFh
(read only)
FFFF 0000h _{On-chip ROM (program ROM)}
FFFF FFFFh
(read only)
Notes: 1. The layout of the address space in boot mode is the same as in single-chip mode.
2. Reserved areas should not be accessed, since the correct operation of LSI is not guaranteed
if they are accessed.
3. For details on the FCU, see section 31, ROM (Flash Memory for Code Storage) and section 32, Data
Flash (Flash Memory for Data Storage) in the User’s manual: Hardware.
Figure 3.1
Memory Map (RX62T Group)
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
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