RX62T_15 Datasheet, PDF (110/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
Table 5.10 Timing of On-Chip Peripheral Modules (2)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol Min.*¹ *²
Max.
Test
Unit Conditions
RIIC
(standard mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rising time
SCL, SDA input falling time
SCL, SDA input spike pulse removal
time
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
6(12) t_llCcyc + 1300
3(6)  t_llCcyc + 300
3(6)  t_llCcyc + 1000
-
-
0
-
ns
-
ns
-
ns
1000
ns
300
ns
1(4) t_llCcyc ns
Figure 5.10
RIIC
(fast mode)
SDA input bus free time
Start condition input hold time
Re-start condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rising time
SCL, SDA input falling time
SCL, SDA input spike pulse removal
time
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
3(6)  t_llCcyc + 300
t_llCcyc + 300
1000
1000
t_llCcyc + 50
0
-
6(12) t_llCcyc + 600
3(6)  t_llCcyc + 300
3(6)  t_llCcyc + 300
20 + 0.1C_b
20 + 0.1C_b
0
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
400
pF
-
ns
-
ns
-
ns
300
ns
300
ns
1(4) t_llCcyc ns
SDA input bus free time
t_BUF
3(6)  t_llCcyc + 300
-
ns
Start condition input hold time
t_STAH
t_llCcyc + 300
-
ns
Re-start condition input setup time
t_STAS
300
-
ns
Stop condition input setup time
t_STOS
300
-
ns
Data input setup time
t_SDAS
t_llCcyc + 50
-
ns
Data input hold time
t_SDAH
0
-
ns
SCL, SDA capacitive load
C_b
-
400
pF
Note: • t_IICcyc: Cycles of internal base clock (IICφ) for the RIIC module
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 110 of 134