RX62T_15 Datasheet, PDF (2/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1
Outline of Specifications (1 / 5)
Classification
CPU
Module/Function
CPU
Memory
FPU
ROM
RAM
Data flash
MCU operating mode
Clock
Clock generation
circuit
Description
 Maximum operating frequency: 100MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system clock)
 Address space: 4-Gbyte linear
 Register set of the CPU
 General purpose: Sixteen 32-bit registers
 Control: Nine 32-bit registers
 Accumulator: One 64-bit register
 Basic instructions: 73
 Floating-point instructions: 8
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
 Instructions: Little endian
 Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 x 32  64 bits
 On-chip divider: 32 / 32  32 bits
 Barrel shifter: 32 bits
 Memory-protection unit (MPU)
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
 ROM capacity: 256 Kbytes (max.)
 Two on-board programming modes
 Boot mode (The user MAT is programmable via the SCI)
 User program mode
 Off-board programming
 A PROM programmer can be used to program the user mat.
 RAM capacity: 16 Kbytes (max.)
 Data flash capacity: 32 Kbytes (max.)
 Supports background operations (BGO)
 Single-chip mode
 One circuit: Main clock oscillator
 Internal oscillator: Low-speed on-chip oscillator dedicated to IWDT
 Structure of a PLL frequency synthesizer and frequency divider for selectable operating
frequency
 Oscillation stoppage detection
 Independent frequency-division and multiplication settings for the system clock (ICLK)
and peripheral module clock (PCLK)
 The CPU and system sections such as other bus masters, MTU3, and GPT run in
synchronization with the system clock (ICLK): 8 to 100 MHz.
 Peripheral modules run in synchronization with the peripheral module clock (PCLK):
8 to 50 MHz
Reset
Pin reset, power-on reset (automatic power-on reset when the power is turned on),
voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and
deep software standby reset
Voltage detection circuit (LVD)
When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Low power
consumption
Low power
consumption
facilities
 Module stop function
 Four low power consumption modes
 Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
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