RX62T_15 Datasheet, PDF (12/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
MPU
Clock
generation
circuit
POR
LVD
MTU3
GPT
ICU
DTC
Data flash
WDT
IWDT
CRC
SCI  3 channels
RSPI
CAN (as an optional function)
LIN
POE3
CMT  2 channels (unit 0)
CMT  2 channels (unit 1)
RIIC
12-bit A/D converter  4 channels (unit 0)
Programmable gain amps
 3 channels
Sample-and-hold circuits
for the pin section  3 channels
Window comparator  3 channels
12-bit A/D converter  4 channels (unit 1)
Programmable gain amps
 3 channels
Sample-and-hold circuits
for the pin section  3 channels
Window comparator  3 channels
10-bit A/D converter  12 chan*n¹ els
*¹
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port D
Port E
Port G
[Legend]
POR: Power-on reset circuit
DTC: Data transfer controller
MTU3: Multi-function timer pulse unit 3
POE3: Port output enable 3
GPT: General PWM timer
CMT: Compare match timer
SCI: Serial communications interface
RIIC: I²C bus interface
MPU: Memory-Protection Unit
CAN: CAN module
LIN: LIN module
RSPI: Renesas serial peripheral interface
LVD: Voltage detection circuit
ICU: Interrupt controller
WDT: Watchdog timer
IWDT: Independent watchdog timer
CRC: CRC (cyclic redundancy check) calculator
Notes: 1. The installation of the 10-bit A/D converter and ports 1 to G is different depending on the package.
2. For details on the internal peripheral bus configuration, see section 12, Buses in the User’s manual:
Hardware.
Figure 1.2
Block Diagram
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
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