RX62T_15 Datasheet, PDF (104/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
5.3 AC Characteristics
Table 5.6
Operation Frequency Value
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Operating
System clock (ICLK)
f
frequency
Peripheral module clock (PCLK)
8
-
8
-
100
MHz
50
5.3.1
Clock Timing
Table 5.7
Clock Timing
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Max.
Unit
Test
Conditions
Oscillation settling time after reset (crystal)
t_OSC1
10
-
Oscillation settling time after leaving software standby mode t_OSC2
10
-
(crystal)
Oscillation settling time after leaving deep software standby t_OSC3
10
-
mode (crystal)
ms
Figure 5.1
ms
Figure 5.2
ms
Figure 5.3
EXTAL external clock output delay settling time
EXTAL external clock input low pulse width
EXTAL external clock input high pulse width
EXTAL external clock rising time
EXTAL external clock falling time
On-chip oscillator (IWDTCLK) oscillation frequency
t_DEXT
t_EXL
t_EXH
t_EXr
t_EXf
f_IWDTCLK
1
35
35
-
-
62.5
-
ms
-
ns
-
ns
5
ns
5
ns
187.5
kHz
Figure 5.1
Figure 5.4
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 104 of 134