RX62T_15 Datasheet, PDF (117/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
ICLK
Input capture
input
t_GTICW
Figure 5.18 GPT Input/Output Timing
Table 5.13 Timing of On-Chip Peripheral Modules (5)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Max.
Unit
Test
Conditions
POE3
POE# input pulse width
t_POEW
1.5
-
t_Pcyc
Figure 5.19
Note: • t_Pcyc: PCLK cycle
PCLK
POEn# input
Figure 5.19 POE3# Clock Timing
t_POEW
5.3.4
Timing of PWM Delay Generation Circuit
Table 5.14 Timing of the PWM Delay Generation Circuit
Note: Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = VREL0 = 0 V
AVCC = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr.
Item
Resolution
DNL*¹
Symbol
Typ.
Max.
Unit
—
312.5
—
ps
—
2.0
—
LSB
Test Conditions
ICLK = 100 MHz
Note 1. This value is correct when the difference between each code and the next is a resolution of one bit (1 LSB).
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 117 of 134