RX62T_15 Datasheet, PDF (108/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
5.3.2
Control Signal Timing
Table 5.8
Control Signal Timing
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
RES# pulse width
(except for programming or erasure of the ROM or data-flash
memory or blank checking of the data-flash memory*¹)
Internal reset time*³
NMI pulse width
IRQ pulse width
Symbol
t_RESW*²
t_RESW2
t_NMIW
t_IRQW
Min.
20
1.5
35
200
200
Max.
-
-
-
-
-
Unit
t_Icyc*⁴
s
s
ns
ns
Test
Conditions
Figure 5.5
Figure 5.6
Figure 5.7
Note 1. For a reset by the signal on the RES# pin during programming or erasure of the ROM or data-flash memory or during blank
checking of the data-flash memory, see section 31.12, Usage Notes in section 31, ROM (Flash Memory for Code Storage) in the
User’s manual: Hardware.
Note 2. Both the time and the number of cycles should satisfy the specifications.
Note 3. This is to specify the FCU reset.
Note 4. ICLK cycles.
RES#
Figure 5.5
Reset Input Timing
t_RESW
NMI
Figure 5.6
NMI Interrupt Input Timing
t_NMIW
IRQ
Figure 5.7
IRQ Interrupt Input Timing
t_IRQW
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 108 of 134