RX62T_15 Datasheet, PDF (42/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
(4) Number of Access Cycles to I/O Registers
The number of access cycles to I/O registers is obtained by following equation.*
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided cycles for clock synchronization +
Number of bus cycles for internal peripheral buses 1, 2, 4, and 6
The number of bus cycles for internal peripheral buses 1, 2, 4, and 6 differs according to the register to be accessed. For
the number of access cycles to each I/O register, see Table 4.1, List of I/O Registers.
When peripheral functions connected to internal peripheral bus 6 are accessed, the number of divided cycles for clock
synchronization is added.
Although the number of divided cycles for clock synchronization differs depending on the number of frequency ratio
between ICLK and PCLK or bus access timing, the sum of the number of bus cycles for internal main bus 1 and the
number of divided cycles for clock synchronization will be one PCLK at a maximum. Therefore, one PCLK is added to
the number of access cycles shown in Table 4.1.
Note: • This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching
to the external memory or bus access from the different bus master (DTC).
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 42 of 134