RX62T_15 Datasheet, PDF (4/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1. Overview
Table 1.1
Outline of Specifications (3 / 5)
Classification
Timers
Communications
Module/Function
General PWM timer
(GPT/GPTa)
Compare match
timer (CMT)
Watchdog timer
(WDT)
Independent
watchdog
timer (IWDT)
Serial
communications
interface (SCIb)
I²C bus interface
(RIIC)
Description
 16 bits x 4 channels
 Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
 Clock sources independently selectable for all channels
 2 input/output pins per channel
 2 output compare/input capture registers per channel
 For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
 In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
 Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
 Synchronizable operation of the several counters
 Modes of synchronized operation (synchronized, or displaced by desired times for phase
shifting)
 Generation of dead times in PWM operation
 Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
 Starting, clearing, and stopping counters in response to external or internal triggers
 Internal trigger sources: output of the internal comparator detection, software, and
compare-match
 The frequency-divided system clock (ICLK) can be used as a counter clock for
measuring timing of the edges of signals produced by frequency-dividing the low-speed
on-chip oscillator clock signal dedicated to IWDT (to detect abnormal oscillation).
 PWM delay generation can control the timing with which signals on the two PWM output
pins for each channel rise and fall with an accuracy of up to 1/32 times the period of the
system clock (ICLK) (only for GPTa).
 (16 bits x 2 channels) x 2 units
 Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 8 bits x 1 channel
 Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
 Switchable between watchdog timer mode and interval timer mode
 14 bits x 1 channel
 Counter-input clock: low-speed on-chip oscillator dedicated to IWDT
 3 channels
 Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
 Multiprocessor communications
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB-first or MSB-first transfer
 Noise cancellation (only available in asynchronous mode)
 1 channel
 Communications formats
I²C bus format/SMBus format
Master/slave selectable
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
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