RX62T_15 Datasheet, PDF (125/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
5.7 ROM (Flash Memory for Code Storage) Characteristics
Table 5.21 ROM (Flash Memory for Code Storage) Characteristics (1)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Temperature range for the programming/erasure operation:
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Rewrite/erase cycle*1
Data hold time
Symbol
N_PEC
t_DRP
Min.
1000
30^*2
Typ.
—
—
Max.
—
—
Unit
Times
Year
Test Conditions
Ta = +85C°
Note 1. Definition of rewrite/erase cycle:
The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 1000), erasing can
be performed n times for each block. For instance, when 256-byte writing is performed 16 times for different addresses in 4-
Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address
for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 5.22 ROM (Flash Memory for Code Storage) Characteristics (2)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Temperature range for the programming/erasure operation:
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Programming time 256 bytes
t_P256
—
4 Kbytes
t_P4K
—
16 Kbytes
t_P16K
—
256 byte
t_P256
—
4 Kbytes
t_P4K
—
16 Kbytes
t_P16K
—
Erasure time
4 Kbytes
t_E4K
—
16 Kbytes
t_E16K
—
4 Kbytes
t_E4K
—
16 Kbytes
t_E16K
—
Suspend delay time during writing
t_SPD
—
First suspend delay time during
t_SESD1
—
erasing (in suspend priority mode)
2
12
ms
23
50
ms
90
200
ms
2.4
14.4
ms
27.6
60
ms
108
240
ms
25
60
ms
100
240
ms
30
72
ms
120
288
ms
—
120
s
—
120
s
PCLK = 50 MHz
N_PEC  100
PCLK = 50 MHz
N_PEC > 100
PCLK = 50 MHz
N_PEC  100
PCLK = 50 MHz
N_PEC > 100
Figure 5.24
PCLK = 50 MHz
Second suspend delay time during
t_SESD2
—
—
1.7
ms
erasing (in suspend priority mode)
Suspend delay time during erasing
t_SEED
—
—
1.7
ms
(in erasure priority mode)
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 125 of 134