RX62T_15 Datasheet, PDF (116/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
Table 5.12 Timing of On-Chip Peripheral Modules (4)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
MTU3
GPT
Input capture input pulse width
(single-edge setting)
Input capture input pulse width
(both-edge setting)
Timer clock pulse width
(single-edge setting)
Timer clock pulse width
(both-edge setting)
Timer clock pulse width
(phase coefficient mode)
Input capture input pulse width
(single-edge setting)
Input capture input pulse width
(both-edge setting)
Symbol
t_TICW
t_TICW
t_TCKWH/L
t_TCKWH/L
t_TCKWH/L
t_GTICW
t_GTICW
Min.
3.0
5.0
3.0
5.0
5.0
3.0
5.0
Max.
-
-
-
-
-
-
-
Unit
t_Icyc
t_Icyc
t_Icyc
t_Icyc
t_Icyc
t_Icyc
t_Icyc
Test
Conditions
Figure 5.16
Figure 5.17
Figure 5.18
Note: • t_Icyc: ICLK cycle
ICLK
Input capture
input
t_TICW
Figure 5.16 MTU3 Input/Output Timing
ICLK
MTCLKA to
MTCLKD
Figure 5.17
t_TCKWL
MTU3 Clock Input Timing
t_TCKWH
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 116 of 134