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RX62T_15 Datasheet, PDF (57/136 Pages) Renesas Technology Corp – Renesas MCUs
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (15 / 25)
Address
0009 041Ch
0009 0420h
0009 0424h
0009 0428h
0009 042Ch
0009 0820h
to
0009 083Fh
0009 0840h
0009 0842h
0009 0844h
0009 0848h
0009 0849h
0009 084Ah
0009 084Bh
0009 084Ch
0009 084Dh
0009 084Eh
0009 084Fh
0009 0850h
0009 0851h
0009 0852h
0009 0853h
0009 0854h
0009 0856h
0009 0858h
0009 4001h
0009 4002h
0009 4003h
0009 4004h
0009 4008h
0009 4009h
0009 400Ah
0009 400Bh
0009 400Ch
0009 400Dh
0009 400Eh
0009 4010h
0009 4011h
0009 4012h
0009 4013h
0009 4014h
0009 4015h
0009 4016h
0009 4018h
Module
Abbreviation Register Name
CAN0*2
Mask register 7
CAN0*2
FIFO received ID compare register 0
CAN0*2
FIFO received ID compare register 1
CAN0*2
Mask invalid register
CAN0*2
Mailbox interrupt enable register
CAN0*2
Message control registers 0 to 31
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
CAN0*2
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
LIN0
Control register
Status register
Bit configuration register
Receive FIFO control register
Receive FIFO pointer control register
Transmit FIFO control register
Transmit FIFO pointer control register
Error interrupt enable register
Error interrupt factor judge register
Receive error count register
Transmit error count register
Error code store register
Channel search support register
Mailbox search status register
Mailbox search mode register
Time stamp register
Acceptance filter support register
Test control register
LIN wake-up baud rate select register
LIN baud rate prescaler 0 register
LIN baud rate prescaler 1 register
LIN self-test control register
Mode register
Break field setting register
Space setting register
Wake-up setting register
Interrupt enable register
Error detection enable register
Control register
Transmission control register
Mode status register
Status register
Error status register
Response field set register
Buffer register
Check sum buffer register
Data 1 buffer register
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Register
Number Access
Abbreviation of Bits Size
Number of
Access
Cycles
MKR7
32
8, 16, 32 2, 3 PCLK*3
FIDCR0
32
8, 16, 32 2, 3 PCLK*3
FIDCR1
32
8, 16, 32 2, 3 PCLK*3
MKIVLR
32
8, 16, 32 2, 3 PCLK*3
MIER
32
8, 16, 32 2, 3 PCLK*3
MCTL0
8
8
2, 3 PCLK*3
to
MCTL31
CTLR
16
8, 16
2, 3 PCLK*3
STR
16
8, 16
2, 3 PCLK*3
BCR
32
8, 16, 32 2, 3 PCLK*3
RFCR
8
8
2, 3 PCLK*3
RFPCR
8
8
2, 3 PCLK*3
TFCR
8
8
2, 3 PCLK*3
TFPCR
8
8
2, 3 PCLK*3
EIER
8
8
2, 3 PCLK*3
EIFR
8
8
2, 3 PCLK*3
RECR
8
8
2, 3 PCLK*3
TECR
8
8
2, 3 PCLK*3
ECSR
8
8
2, 3 PCLK*3
CSSR
8
8
2, 3 PCLK*3
MSSR
8
8
2, 3 PCLK*3
MSMR
8
8
2, 3 PCLK*3
TSR
16
8, 16
2, 3 PCLK*3
AFSR
16
8, 16
2, 3 PCLK*3
TCR
8
8
2, 3 PCLK*3
LWBR
8
8
2, 3 PCLK*3
LBRP0
8
8, 16
2, 3 PCLK*3
LBRP1
8
8, 16
2, 3 PCLK*3
LSTC
8
8
2, 3 PCLK*3
L0MD
8
8, 16, 32 2, 3 PCLK*3
L0BRK
8
8, 16, 32 2, 3 PCLK*3
L0SPC
8
8, 16, 32 2, 3 PCLK*3
L0WUP
8
8, 16, 32 2, 3 PCLK*3
L0IE
8
8, 16
2, 3 PCLK*3
L0EDE
8
8, 16
2, 3 PCLK*3
L0C
8
8
2, 3 PCLK*3
L0TC
8
8, 16, 32 2, 3 PCLK*3
L0MST
8
8, 16, 32 2, 3 PCLK*3
L0ST
8
8, 16, 32 2, 3 PCLK*3
L0EST
8
8, 16, 32 2, 3 PCLK*3
L0RFC
8
8, 16
2, 3 PCLK*3
L0IDB
8
8, 16
2, 3 PCLK*3
L0CBR
8
8
2, 3 PCLK*3
L0DB1
8
8, 16, 32 2, 3 PCLK*3
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