RX62T_15 Datasheet, PDF (40/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
4. I/O Registers
This section gives information on the on-chip I/O register addresses and bit configurations. The information is given as
shown below. Notes on writing to registers are also given at the end.
(1) I/O register addresses (address order)
 Registers are listed from the lower allocation addresses.
 Registers are classified according to functional modules (abbreviations).
 The number of access cycles indicates the number of states based on the specified reference clock.
 Among the I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses must not be
accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent
operations cannot be guaranteed.
 A unit of access is specified for each register. Access other than in the specified unit is prohibited.
(2) I/O register bits
 Bit configurations of the registers are listed in the same order as the register addresses.
 Reserved bits are indicated by "—" in the bit name column.
 Space in the bit name field indicates that the entire register is allocated to either the counter or data.
 For the registers of 16 or 32 bits, the MSB is listed first.
(3) Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
 The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERm of the
ICU (interrupt request enable bit)*¹ cleared to 0.
 A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
Note 1. See section 11.2.2, Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) in the User’s manual:
Hardware.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 40 of 134