RX62T_15 Datasheet, PDF (67/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (25 / 25)
Address
Module
Abbreviation Register Name
Register
Number Access
Abbreviation of Bits Size
Number of
Access
Cycles
007F FFBAh FLASH
FCU command register
FCMDR
16
16
2, 3 PCLK^*3
007F FFC8h FLASH
FCU processing switching register
FCPSR
16
16
2, 3 PCLK^*3
007F FFCAh FLASH
Data flash blank check control register
DFLBCCNT 16
16
2, 3 PCLK^*3
007F FFCCh FLASH
Flash P/E status register
FPESTAT
16
16
2, 3 PCLK^*3
007F FFCEh FLASH
Data flash blank check status register
DFLBCSTAT 16
16
2, 3 PCLK^*3
007F FFE8h FLASH
Peripheral clock notification register
PCKAR
16
16
2, 3 PCLK^*3
Note 1. This register is not supported by the 100-pin LQFP version.
Note 2. This register is not supported by the product without the CAN function.
Note 3. The number of access states depends on the number of divided cycles for clock synchronization (0 to 1 PCLK).
Note 4. Reading the registers takes 3 cycles of ICLK and writing to the registers takes 5 cycles of ICLK.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 67 of 134