RX62T_15 Datasheet, PDF (54/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (12 / 25)
Address
0008 90A4h
0008 90A6h
0008 90B0h
0008 90E0h
0008 C001h
0008 C002h
0008 C003h
0008 C007h
0008 C008h
0008 C009h
0008 C00Ah
0008 C00Bh
0008 C00Dh
0008 C00Eh
0008 C010h
0008 C021h
0008 C022h
0008 C023h
0008 C027h
0008 C028h
0008 C029h
0008 C02Ah
0008 C02Bh
0008 C02Dh
0008 C02Eh
0008 C030h
0008 C041h
0008 C042h
0008 C043h
0008 C044h
0008 C045h
0008 C046h
0008 C047h
0008 C048h
0008 C049h
0008 C04Ah
0008 C04Bh
0008 C04Dh
0008 C04Eh
0008 C050h
0008 C061h
0008 C062h
0008 C063h
0008 C064h
Module
Abbreviation Register Name
S12AD1
A/D data register 2
S12AD1
A/D data register 3
S12AD1
A/D data register 0B
S12AD1
A/D sampling state register
PORT1
Data direction register
PORT2
Data direction register
PORT3
Data direction register
PORT7
Data direction register
PORT8
Data direction register
PORT9
Data direction register
PORTA
Data direction register
PORTB
Data direction register
PORTD
Data direction register
PORTE
Data direction register
PORTG
Data direction register
PORT1
Data register
PORT2
Data register
PORT3
Data register
PORT7
Data register
PORT8
Data register
PORT9
Data register
PORTA
Data register
PORTB
Data register
PORTD
Data register
PORTE
Data register
PORTG
Data register
PORT1
Data register
PORT2
Data register
PORT3
Data register
PORT4
Data register
PORT5
Data register
PORT6
Data register
PORT7
Data register
PORT8
Data register
PORT9
Data register
PORTA
Data register
PORTB
Data register
PORTD
Data register
PORTE
Data register
PORTG
Port register
PORT1
Input buffer control register
PORT2
Input buffer control register
PORT3
Input buffer control register
PORT4
Input buffer control register
Register
Number Access
Abbreviation of Bits Size
ADDR2
16
16
ADDR3
16
16
ADDR0B
16
16
ADSSTR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR
8
8
DDR*¹
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR
8
8
DR*¹
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT
8
8
PORT*¹
8
8
ICR
8
8
ICR
8
8
ICR
8
8
ICR
8
8
Number of
Access
Cycles
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
2, 3 PCLK*³
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 54 of 134