RX62T_15 Datasheet, PDF (126/136 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
5. Electrical Characteristics
5.8 Data Flash (Flash Memory for Data Storage) Characteristics
Table 5.23 Data Flash (Flash Memory for Data Storage) Characteristics (1)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Temperature range for the programming/erasure operation:
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Rewrite/erase cycle*1
Data hold time
Symbol
N_DPEC
t_DDRP
Min.
30000
30^*2
Typ.
—
—
Max.
—
—
Unit
Times
Year
Test Conditions
Ta = +85C°
Note 1. Definition of rewrite/erase cycle:
The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 30000), erasing can
be performed n times for each block. For instance, when 128-byte writing is performed 16 times for different addresses in 2-
Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address
for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 5.24 Data Flash (Flash Memory for Data Storage) Characteristics (2)
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Temperature range for the programming/erasure operation:
Ta = Topr. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Programming time
Erasure time
8 bytes
t_DP8
—
128 bytes
t_DP128
—
2 Kbytes
t_DE2K
—
0.4
2
1
5
ms
PCLK =
ms
50 MHz
70
250
ms
PCLK =
50 MHz
Blank check time
8 bytes
t_DBC8
—
—
30
s
PCLK =
2 Kbytes
t_DBC2K
—
—
0.7
ms
50 MHz
Suspend delay time during writing
t_DSPD
—
—
120
s
Figure 5.24
First suspend delay time during erasing t_DSESD1
—
(in suspend priority mode)
—
120
s
PCLK =
50 MHz
Second suspend delay time during
t_DSESD2
—
—
1.7
ms
erasing (in suspend priority mode)
Suspend delay time during erasing
t_DSEED
—
—
1.7
ms
(in erasure priority mode)
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 126 of 134