RX63N_15 Datasheet, PDF (82/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (3/50)
Address
0008 2818h
0008 281Ch
0008 281Dh
0008 281Eh
0008 2820h
0008 2821h
0008 2822h
0008 2840h
0008 2844h
0008 2848h
0008 284Ch
0008 2850h
0008 2852h
0008 2853h
0008 2854h
0008 285Ch
0008 285Dh
0008 285Eh
0008 2860h
0008 2861h
0008 2862h
0008 2A00h
0008 2BE0h
0008 2BE4h
0008 2BE8h
0008 2BECh
0008 2BF0h
0008 2BF4h
0008 2BF8h
0008 2BFCh
0008 3002h
0008 3004h
0008 3008h
0008 3012h
0008 3014h
0008 3018h
0008 3022h
0008 3024h
0008 3028h
0008 3032h
0008 3034h
0008 3038h
0008 3042h
0008 3044h
0008 3048h
0008 3052h
0008 3054h
0008 3058h
0008 3062h
0008 3064h
0008 3068h
Module
Symbol
EXDMAC0
EXDMAC0
EXDMAC0
EXDMAC0
EXDMAC0
EXDMAC0
EXDMAC0
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC1
EXDMAC
EXDMAC
EXDMAC
EXDMAC
EXDMAC
EXDMAC
EXDMAC
EXDMAC
EXDMAC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
Register Name
EXDMA offset register
EXDMA transfer enable register
EXDMA software start register
EXDMA status register
EXDMA external request sense mode register
EXDMA external request flag register
EXDMA peripheral request flag register
EXDMA source address register
EXDMA destination address register
EXDMA transfer count register
EXDMA block transfer count register
EXDMA transfer mode register
EXDMA output setting register
EXDMA interrupt setting register
EXDMA address mode register
EXDMA transfer enable register
EXDMA software start register
EXDMA status register
EXDMA external request sense mode register
EXDMA external request flag register
EXDMA peripheral request flag register
EXDMA module start register
Cluster buffer register 0
Cluster buffer register 1
Cluster buffer register 2
Cluster buffer register 3
Cluster buffer register 4
Cluster buffer register 5
Cluster buffer register 6
Cluster buffer register 7
CS0 mode register
CS0 wait control register 1
CS0 wait control register 2
CS1 mode register
CS1 wait control register 1
CS1 wait control register 2
CS2 mode register
CS2 wait control register 1
CS2 wait control register 2
CS3 mode register
CS3 wait control register 1
CS3 wait control register 2
CS4 mode register
CS4 wait control register 1
CS4 wait control register 2
CS5 mode register
CS5 wait control register 1
CS5 wait control register 2
CS6 mode register
CS6 wait control register 1
CS6 wait control register 2
Register
Symbol
EDMOFR
EDMCNT
EDMREQ
EDMSTS
EDMRMD
EDMERF
EDMPRF
EDMSAR
EDMDAR
EDMCRA
EDMCRB
EDMTMD
EDMOMD
EDMINT
EDMAMD
EDMCNT
EDMREQ
EDMSTS
EDMRMD
EDMERF
EDMPRF
EDMAST
CLSBR0
CLSBR1
CLSBR2
CLSBR3
CLSBR4
CLSBR5
CLSBR6
CLSBR7
CS0MOD
CS0WCR1
CS0WCR2
CS1MOD
CS1WCR1
CS1WCR2
CS2MOD
CS2WCR1
CS2WCR2
CS3MOD
CS3WCR1
CS3WCR2
CS4MOD
CS4WCR1
CS4WCR2
CS5MOD
CS5WCR1
CS5WCR2
CS6MOD
CS6WCR1
CS6WCR2
Number Access
of Bits Size
32
32
8
8
8
8
8
8
8
8
8
8
8
8
32
32
32
32
32
32
16
16
16
16
8
8
8
8
32
32
8
8
8
8
8
8
8
8
8
8
8
8
8
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
16
16
32
32
32
32
Number of Access States
Related
ICLKPCLK ICLK<PCLK Function
1, 2 BCLK
EXDMACa
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
Buses
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
1, 2 BCLK
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 82 of 208