RX63N_15 Datasheet, PDF (169/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.24 Timing of On-Chip Peripheral Modules (6)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Symbol Min.*^, *²
Max.*
Unit
Test
Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
6(12) × t_IICcyc + 240
3(6) × t_IICcyc + 120
3(6) × t_IICcyc + 120
—
—
0
3(6) × t_IICcyc + 120
t_IICcyc + 120
120
120
t_IICcyc + 120
0
—
—
—
0
250
0
—
20 + 0.1C_b
20 + 0.1C_b
0
100
0
—
—
ns Figure
—
ns ^5.47
—
ns
120
ns
120
ns
1(4) × t_IICcyc ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
550
pF
1000
ns
300
ns
4 × t_IICcyc
ns
—
ns
—
ns
400
pF
300
ns
300
ns
4 × t_IICcyc
ns
—
ns
—
ns
400
pF
Note: t_IICcyc: RIIC internal reference clock (IIC) Cycle, t_Pcyc: PCLK cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 169 of 208