RX63N_15 Datasheet, PDF (171/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.26 Timing of On-Chip Peripheral Modules (8)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.7V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0V, PIXCLK = 27MHz, T_a = T_opr
PDC
Item
VSYNC/HSYNC input setup time
VSYNC/HSYNC input hold time
PIXD input setup time
PIXD input hold time
PIXCLK input cycle time
PIXCLK input pulse width high level
PIXCLK input pulse width low level
PCKO pin output cycle time
PCKO pin output high level pulse width
PCKO pin output low level pulse width
PCKO pin output rising time
PCKO pin output falling time
Symbol
t_SYNCSETUP
t_SYNCHOLD
t_DATASETUP
t_DATAHOLD
t_PIXcyc
t_PIXH
t_PIXL
t_PCKcyc
t_PCKH
t_PCKL
t_PCKr
t_PCKf
min
10
5
10
5
37
10
10
40
13
13
—
—
typ
—
—
—
—
—
—
—
—
—
—
—
—
max
—
—
—
—
1000
—
—
1000
—
—
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Figure 5.58
Figure 5.59
Figure 5.60
PCLK
Port
Figure 5.34 I/O Port Input Timing
PCLK
Output compare
output
Input capture
input
Figure 5.35 MTU Input/Output Timing
t_PRW
t_TICW
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 171 of 208