RX63N_15 Datasheet, PDF (129/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (50/50)
Address
Module
Symbol
007F C402h FLASH
007F C410h FLASH
007F C411h FLASH
007F C412h FLASH
007F C440h FLASH
007F C442h FLASH
007F C450h FLASH
007F C452h FLASH
007F C454h FLASH
007F FFB0h FLASH
007F FFB1h FLASH
007F FFB2h FLASH
007F FFB4h FLASH
007F FFB6h FLASH
007F FFBAh FLASH
007F FFC8h FLASH
007F FFCAh FLASH
007F FFCCh FLASH
007F FFCEh FLASH
007F FFE8h FLASH
FEFF FAC0h FLASH
FEFF FAC1h FLASH
FEFF FAC2h FLASH
FEFF FAC3h FLASH
FEFF FAC4h FLASH
FEFF FAC5h FLASH
FEFF FAC6h FLASH
FEFF FAC7h FLASH
FEFF FAC8h FLASH
FEFF FAC9h FLASH
FEFF FACAh FLASH
FEFF FACBh FLASH
FEFF FACCh FLASH
FEFF FACDh FLASH
FEFF FACEh FLASH
FEFF FACFh FLASH
FEFF FAD2h TEMPS
FEFF FAD3h TEMPS
Register Name
Flash mode register
Flash access status register
Flash access error interrupt enable register
Flash ready interrupt enable register
E2 DataFlash read enable register 0
E2 DataFlash read enable register 1
E2 DataFlash P/E enable register 0
E2 DataFlash P/E enable register 1
FCU RAM enable register
Flash status register 0
Flash status register 1
Flash P/E mode entry register
Flash protection register
Flash reset register
FCU command register
FCU processing switching register
E2 data flash blank check control register
Flash P/E status register
E2 DataFlash blank check status register
Peripheral clock notification register
Unique ID register 0*⁸
Unique ID register 1*⁸
Unique ID register 2*⁸
Unique ID register 3*⁸
Unique ID register 4*⁸
Unique ID register 5*⁸
Unique ID register 6*⁸
Unique ID register 7*⁸
Unique ID register 8*⁸
Unique ID register 9*⁸
Unique ID register 10*⁸
Unique ID register 11*⁸
Unique ID register 12*⁸
Unique ID register 13*⁸
Unique ID register 14*⁸
Unique ID register 15*⁸
Temperature sensor calibration data register*⁸
Temperature sensor calibration data register*⁸
Register
Symbol
FMODR
FASTAT
FAEINT
FRDYIE
DFLRE0
DFLRE1
DFLWE0
DFLWE1
FCURAME
FSTATR0
FSTATR1
FENTRYR
FPROTR
FRESETR
FCMDR
FCPSR
DFLBCCNT
FPESTAT
DFLBCSTAT
PCKAR
UIDR0
UIDR1
UIDR2
UIDR3
UIDR4
UIDR5
UIDR6
UIDR7
UIDR8
UIDR9
UIDR10
UIDR11
UIDR12
UIDR13
UIDR14
UIDR15
TSCDRL
TSCDRH
Number Access
of Bits Size
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Number of Access States
Related
ICLKPCLK ICLK<PCLK Function
2 to 4 FCLK 2, 3 ICLK Flash Memory
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
2 to 4 FCLK 2, 3 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
1 ICLK
Temperature
sensor
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively.
When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively.
When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 27.4 lists
register allocation for 16-bit access in the User’s manual: Hardware.
When the register is accessed while the USB is operating, a delay may be generated in accessing.
The addresses with odd number cannot be accessed in 16-bit units. 16-bit access to a register should be made to the addresses of the TMOCNTL register. Allocation of
registers to be accessed in 16-bit units is described in the Table 36.6, Allocation of Registers to be Accessed in 16-bit Units in the User’s manual: Hardware.
These registers are only present in the G version.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 129 of 208