RX63N_15 Datasheet, PDF (22/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
1. Overview
Table 1.4
Pin Functions (4/6)
Classifications
Serial communications
interface (SCId)
I²C bus interface
Ethernet controller
Pin Name
I/O
Description
 Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for clock signals.
RXD12
Input
Input pin for data reception.
TXD12
Output Output pin for data transmission.
CTS12#
Input
Transmit/receive start control input pins
RTS12#
Output Transmit/receive start control output pins
 Simple I²C mode
SSCL12
I/O
Input/output pins for the I²C clock
SSDA12
I/O
Input/output pins for the I²C data
 Simple SPI mode
SCK12
I/O
Input/output pins for the clock
SMISO12
I/O
Input/output pins for slave transmit data.
SMOSI12
I/O
Input/output pins for master transmit data.
SS12#
Input
Input pins for chip select signals
 Extended serial mode
RXDX12
Input
Input pin for receive data
TXDX12
Output Output pin for transmit data
SIOX12
I/O
Input/output pin for Transmit/receive data
SCL0[FM+],
SCL1 to SCL3
I/O
Input/output pin for clocks. Bus can be directly driven by the
N-channel open drain output.
SDA0[FM+],
SDA1 to SDA3
I/O
Input/output pin for data. Bus can be directly driven by the
N-channel open drain output.
REF50CK
Input
50-MHz reference clock. This pin inputs reference signals for
transmission/reception timings in RMII mode.
RMII_CRS_DV
Input
Indicates that there are carrier detection signals and valid
receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.
RMII_TXD0, RMII_TXD1
Output 2-bit transmit data in RMII mode.
RMII_RXD0, RMII_RXD1
Input
2-bit receive data in RMII mode.
RMII_TXD_EN
Output Output pin for data transmit enable signals in RMII mode.
RMII_RX_ER
Input
Indicates an error has occurred during reception of data in RMII
mode.
ET_CRS
Input
Carrier detection/data reception enable pin.
ET_RX_DV
Input
Indicates that there are valid receive data on ET_ERXD3 to
ET_ERXD0.
ET_EXOUT
Output General-purpose external output pin.
ET_LINKSTA
Input
Inputs link status from the PHY-LSI.
ET_ETXD0 to ET_ETXD3
Output 4 bits of MII transmit data.
ET_ERXD0 to ET_ERXD3 Input
4 bits of MII receive data.
ET_TX_EN
Output Transmit enable pin. Indicates that transmit data is ready on
ET_ETXD3 to ET_ETXD0.
ET_TX_ER
Output Transmit error pin. Notifies the PHY_LSI of an error during
transmission.
ET_RX_ER
Input
Receive error pin. Recognizes an error during reception.
ET_TX_CLK
Input
Transmit clock pin. This pin inputs reference signals for output
timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and
ET_TX_ER.
ET_RX_CLK
Input
Receive clock pin. This pin inputs reference signals for input
timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and
ET_RX_ER.
ET_COL
Input
Inputs collision detection signals.
ET_WOL
Output Receives Magic packets.
ET_MDC
Output Outputs reference clock signals for information transfer via
ET_MDIO.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 22 of 208