RX63N_15 Datasheet, PDF (141/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
5.3.2
Clock Timing
Table 5.12 Clock Timing (Except for Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V_BATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T_a = T_opr
Item
Symbol
Min.
Typ.
BCLK pin output cycle time
Packages with 177 to 144 t_Bcyc
pins
Packages with 100 pins or
less
20
—
40
—
BCLK pin output high pulse width
BCLK pin output low pulse width
BCLK pin output rising time
BCLK pin output falling time
SDCLK pin output cycle time
only 177 to 144 pin
SDCLK pin output high pulse width
SDCLK pin output low pulse width
SDCLK pin output rising time
SDCLK pin output falling time
EXTAL external clock input cycle time
EXTAL external clock input high pulse width
EXTAL external clock input low pulse width
EXTAL external clock rising time
EXTAL external clock falling time
EXTAL external clock input wait time*¹
Main clock frequency
Main clock oscillator start-up time
Main clock oscillation stabilization wait time
LOCO and IWDTCLK clock cycle time
LOCO and IWDTCLK clock oscillation frequency
LOCO and IWDTCLK clock oscillation stabilization wait time
HOCO clock oscillator oscillation frequency
HOCO clock oscillation stabilization wait time 1*²
HOCO clock oscillation stabilization wait time 2
HOCO clock power supply settling time
PLL clock frequency
PLL lock time
PLL clock oscillation stabilization
wait time
PLL operation started
after main clock
oscillation has settled
t_CH
5
—
t_CL
5
—
t_Cr
—
—
t_Cf
—
—
t_Bcyc
20
—
t_CH
5
—
t_CH
5
—
t_CH
—
—
t_CH
—
—
t_EXcyc
50
—
t_EXH
20
—
t_EXL
20
—
t_EXr
—
—
t_EXf
—
—
t_EXWT
1
—
f_MAIN
4
—
t_MAINOSC
—
—
t_MAINOSCWT —
—
t_cyc
6.96
8
f_LOCO
106.25 125
t_LOCOWT
—
—
f_HOCO
45
50
t_HOCOWT1
—
—
t_HOCOWT2
—
—
t_HOCOP
—
—
f_PLL
104
—
t_PLL1
—
—
t_PLLWT1
—
—
PLL lock time
PLL operation started
before main clock
t_PLL2
—
—
PLL clock oscillation stabilization
oscillation has settled
t_PLLWT2
—
—
wait time
Max.
—
Unit
Test
Conditions
ns
Figure 5.3
—
ns
—
—
5
5
—
—
—
5
5
—
—
—
5
5
—
16
—*³
—*⁴
9.4
143.75
20
55
1.8
2.0
1
200
500
—*⁵
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
MHz
ms
ms
µs
kHz
µs
MHz
ms
ms
ms
MHz
µs
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10
ms
t_MAINOSC
+t_PLL1
ms
—*⁵
ms
Figure 5.11
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 141 of 208