RX63N_15 Datasheet, PDF (163/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
5.3.6
EXDMAC Timing
Table 5.18 EXDMAC Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz, BCLK pin = 8 to 100 MHz, SDCLK pin = 8 to 50 MHz, T_a = T_opr
High drive output is selected by the drive capacity control register
Item
EXDMAC
EDREQ setup time
EDREQ hold time
EDACK delay time
Symbol
t_EDRQS
t_EDRQH
t_EDACD
Min.
20
5
—
Max.
—
—
15
Unit
Test
Conditions
ns
Figure 5.31
ns
Figure 5.32
ns
and
Figure 5.33
BCLK pin
EDREQ0
EDREQ1
t_EDRQS t_EDRQH
Figure 5.31 EDREQ0 and EDREQ1 Input Timing
BCLK pin
EDACK0
EDACK1
t_EDACD
t_EDACD
Figure 5.32 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
BCLK pin
EDACK0
EDACK1
t_EDACD
t_EDACD
Figure 5.33 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 163 of 208