RX63N_15 Datasheet, PDF (50/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
1. Overview
Table 1.7
List of Pins and Pin Functions (145-Pin TFLGA) (5/5)
Pin No.
Timers
Communications
145-pin
TFLGA
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
(ETHERC, SCIc, SCId,
(MTU, TPU, TMR, PPG, RSPI, RIIC, CAN, IEB,
RTC, POE)
USB, and PDC)
Interrupt
S12AD
AD
DA
N7
TRDATA3
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
CRX1/ET_EXOUT
IRQ10
N8
VSS
N9
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TXD8/SMOSI8/SSDA8/
IRQ14
TIOCB6/TMO2/PO31 MISOA/ET_COL
N10
TRSYNC
P82
EDREQ1
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10/
ET_ETXD1/RMII_TXD1
N11
PC3
A19
MTIOC4D/TCLKB/PO24 TXD5/SMOSI5/SSDA5/
IETXD/ET_TX_ER
N12
P75
CS5#
PO20
SCK11/ET_ERXD0/
RMII_RXD0
N13
P74
CS4#
PO19
CTS11#/RTS11#/SS11#/
ET_ERXD1/RMII_RXD1
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 50 of 208