RX63N_15 Datasheet, PDF (139/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.10 Operation Frequency Value (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V_BATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T_a = T_opr
Operation
frequency
Item
Symbol Min.
System clock (ICLK)
f
32
Peripheral module clock (PCLKA)
—
Peripheral module clock (PCLKB)
—
FlashIF clock (FCLK)
32
External bus clock (BCLK) Packages with 177 to 144 pins
—
Packages with 100 pins or less
—
BCLK pin output
Packages with 177 to 144 pins
—
Packages with 100 pins or less
—
SDRAM clock (SDCLK)
Packages with 177 to 144 pins
—
only
SDCLK pin output
Packages with 177 to 144 pins
—
only
USB clock (UCLK)
—
IEBUS clock (IECLK)
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
Unit
143.75 kHz
143.75
143.75
143.75
143.75
143.75
143.75
143.75
143.75
143.75
143.75
143.75
5.3.1
Reset Timing
Table 5.11 Reset Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V_BATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T_a = T_opr
Item
Symbol Min.
RES# pulse
width
Power-on
Deep software standby mode
Software standby mode, low-speed
operating mode 2
t_RESWP
2
t_RESWD
1
t_RESWS
1
Programming or erasure of the ROM or E2 t_RESW
200
data-flash memory or blank checking of the
E2 DataFlash memory
Other than above
Wait time after RES# cancellation
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
t_RESW
200
t_RESWT
59
t_RESW2
112
Typ.
—
—
—
—
—
—
—
Max.
Unit
—
ms
—
ms
—
ms
—
µs
Test
Conditions
Figure 5.1
Figure 5.2
—
µs
60
t_cyc
Figure 5.1
120
t_cyc
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 139 of 208