RX63N_15 Datasheet, PDF (20/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
Table 1.4
Pin Functions (2/6)
Classifications
Bus control
Pin Name
RD#
WR#
WR0# to WR3#
BC0# to BC3#
ALE
CKE
SDCS#
RAS#
CAS#
WE#
DQM0 to DQM3
CS0# to CS7#
WAIT#
EXDMA controller
Interrupt
Multi-function timer pulse
unit 2
EDREQ0, EDREQ1
EDACK0, EDACK1
NMI
IRQ0 to IRQ15
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
MTIOC1A, MTIOC1B
MTIOC2A, MTIOC2B
Port output enable 2
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
MTIC5U, MTIC5V
MTIC5W
MTCLKA, MTCLKB
MTCLKC, MTCLKD
POE0# to POE3#
POE8#
1. Overview
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
Input
Input
Description
Strobe signal which indicates that reading from the external bus
interface space is in progress.
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode.
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
writing to the external bus interface space, in byte strobe mode.
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
access to the external bus interface space, in 1-write strobe
mode.
Address latch signal when address/data multiplexed bus is
selected.
Output pin for SDRAM clock enable signals.
Output pin for SDRAM chip select signals.
Output pin for SDRAM row address strobe signals.
Output pin for SDRAM column address strobe signals.
Output pin for SDRAM write enable signals.
Output pins for SDRAM I/O data mask enable signals.
Select signals for CS area.
Input pins for wait request signals in access to the external
space.
Input pins for external DMA transfer requests.
Output pins for single address transfer acknowledge signals.
Non-maskable interrupt request signal.
Maskable interrupt request signals.
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins.
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins.
Input pins for external clock signals.
Input
Input pins for request signals to place the MTU large-current
pins in the high impedance state.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 20 of 208