RX63N_15 Datasheet, PDF (151/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
BCLK pin
Address bus
Address bus/
data bus
Address latch
(ALE)
Data read
(RD#)
Chip select
(CS1#)
Address cycle
Data cycle
Ta1
TW1
Ta1
TW2
Tan
TW3
TW4
T_W5
Tend
Tn1
Tn2
tAD
tAD
tAD
tALED
tALED
tRDS tRDH
tCSD
t_RSD
tRSD
tCSD
Figure 5.17 Address/Data Multiplexed Bus Read Access Timing
BCLK pin
Address bus
Address bus/
data bus
Address latch
(ALE)
Data write
(WRm#)
Chip select
(CS1#)
Address cycle
Ta1
TW1
Ta1
TW2
Tan
TW3
TW4
Data cycle
TW5
Tend
Tn1
Tn2
Tn3
tAD
tAD
tAD
tWDD
tALED
tALED
tWDH
tCSD
tWRD
tWRD
tCSD
Figure 5.18 Address/Data Multiplexed Bus Write Access Timing
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 151 of 208