RX63N_15 Datasheet, PDF (166/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.21 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*¹, VREFH0 = 2.7 V to AVCC0*¹,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Symbol Min.
Max.
Unit*² Test Conditions
RSPI Data output delay
time
Master
Packages
t_OD
—
with 177 to
144 pins
Packages
—
with 100 pins
or less
18
ns
Figure 5.43 to
Figure 5.46
C = 30_PF
30
Slave
Packages
—
with 177 to
144 pins
3 × t_Pcyc + 40
Packages
—
with 100 pins
or less
3 × t_Pcyc + 50
Data output hold
time
Master
Slave
t_OH
0
0
—
ns
—
Successive
transmission delay
time
MOSI and MISO
rise/fall time
Master
Slave
Output
t_TD
t_SPcyc + 2 × t_Pcyc 8 × t_SPcyc
ns
+ 2 × t_Pcyc
4 × t_Pcyc
—
Packages
with 177 to
144 pins
t_Dr, t_Df
—
5
ns
Packages
—
with 100 pins
or less
Input
—
10
1
μs
SSL rise/fall time
Output
Packages
t_SSLr,
—
with 177 to
t_SSLf
144 pins
5
ns
Packages
—
with 100 pins
or less
Input
—
10
1
μs
Slave access time
Slave output release time
t_SA
—
t_REL
—
4
t_Pcyc Figure 5.45 and
3
t_Pcyc
Figure 5.46
C = 30_PF
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t_Pcyc: PCLK cycle
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 166 of 208