RX63N_15 Datasheet, PDF (183/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.29 12-Bit A/D Conversion Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
Item
Min.
Typ.
Resolution
—
—
Conversion AN0 to AN7
time*¹
Permissible signal source impedance 1.0 (0.4)*² —
(max.) = 1.0 kΩ
(Operation
at PCLK = _{Other channels Permissible signal source impedance 2.0 (1.4)*2 —}
50 MHz)
(max.) = 1.0 kΩ, AVCC  3.0 V
Permissible signal source impedance 5.6 (5.0)*² —
(max.) = 1.0 kΩ, AVCC  2.7 V
Analog input capacitance
Offset error
Full-scale error
Quantization error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
—
—
—
±2.0
—
±2.0
—
±0.5
—
±2.5
—
±2.0
—
±2.0
Max.
12
—
—
—
30
±7.5
±7.5
—
±8.0
±4.0
±4.0
Unit
Test
Conditions
Bit
µs Sampling
in 20
states
µs Sampling
in 70
states
µs Sampling
in 250
states
pF
LSB
LSB
LSB
LSB
LSB
LSB
Note: The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.30 A/D Internal Reference Voltage Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
Item
A/D Internal reference voltage
Min.
Typ.
Max.
Unit
Test
Conditions
1.45
1.50
1.55
V
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 183 of 208