RX63N_15 Datasheet, PDF (149/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
5.3.5
Bus Timing
Table 5.16 Bus Timing (packages with 177 to 144 pins)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 100 MHz, BCLK pin = 8 to 50 MHz, SDCLK pin = 8 to 50MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, I_OH = -1.0 mA, I_OL = 1.0 mA, C = 30 pF
High drive output is selected by the drive capacity control register.
Item
Address delay time
Byte control delay time
CS# delay time
ALE delay time
RD# delay time
Read data setup time
Read data hold time
WR# delay time
Write data delay time
Write data hold time
WAIT# setup time
WAIT# hold time
Address delay time 2 (SDRAM)
CS# delay time 2 (SDRAM)
DQM delay time (SDRAM)
CKE delay time (SDRAM)
Read data setup time 2 (SDRAM)
Read data hold time 2 (SDRAM)
Write data delay time 2 (SDRAM)
Write data hold time 2 (SDRAM)
WE# delay time (SDRAM)
RAS# delay time (SDRAM)
CAS# delay time (SDRAM)
Symbol
t_AD
t_BCD
t_CSD
t_ALED
t_RSD
t_RDS
t_RDH
t_WRD
t_WDD
t_WDH
t_WTS
t_WTH
t_AD2
t_CSD2
t_DQMD
t_CKED
t_RDS2
t_RDH2
t_WDD2
t_WDH2
t_WED
t_RASD
t_CASD
Min.
—
—
—
—
—
15
0
—
—
0
15
0
1
1
1
1
12
0
—
1
1
1
1
Max.
Unit
15
ns
15
ns
15
ns
20
ns
15
ns
—
ns
—
ns
15
ns
15
ns
—
ns
—
ns
—
ns
15
ns
15
ns
15
ns
15
ns
—
ns
—
ns
15
ns
—
ns
15
ns
15
ns
15
ns
Test Conditions
Figure 5.17 to
Figure 5.22
Figure 5.23
Figure 5.24 to
Figure 5.30
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 149 of 208