RX63N_15 Datasheet, PDF (167/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.22 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise/fall time
Data input setup time
Data input hold time
SS input setup time
SS input hold time
Data output delay time
Data output hold time
Data rise/fall time
SS input rise/fall time
Slave access time
Slave output release time
Note 1. t_Pcyc: PCLK cycle
Symbol
t_SPcyc
t_SPCKWH
t_SPCKWL
t_SPCKr, t_SPCKf
t_SU
t_H
t_LEAD
t_LAG
t_OD
t_OH
t_Dr, t_Df
t_SSLr, t_SSLf
t_SA
t_REL
Min.
4
8
0.4
0.4
—
40
40
1
1
—
–10
—
—
—
—
Max.
65536
65536
0.6
0.6
20
—
—
—
—
40
—
20
20
5
5
Unit*¹
t_Pcyc
Test Conditions
Figure 5.42
t_SPcyc
t_SPcyc
ns
ns
ns
t_SPcyc
t_SPcyc
ns
ns
ns
ns
t_Pcyc
t_Pcyc
Figure 5.43 to
Figure 5.46
Figure 5.46
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 167 of 208