RX63N_15 Datasheet, PDF (127/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (48/50)
Address
000A 02A0h
Module
Symbol
USB1
Register Name
Pipe 5 transaction counter enable register
Register
Symbol
PIPE5TRE
000A 02A2h USB1
Pipe 5 transaction counter register
PIPE5TRN
000A 0400h USB
Deep standby USB transceiver control/pin monitor
register
DPUSR0R
000A 0404h USB
Deep standby USB suspend/resume interrupt register DPUSR1R
000A 0500h PDC
000A 0504h PDC
000A 0508h PDC
000A 050Ch PDC
000A 0510h PDC
000A 0514h PDC
000A 0518h PDC
000C 0000h EDMAC
000C 0008h EDMAC
000C 0010h EDMAC
000C 0018h EDMAC
000C 0020h EDMAC
000C 0028h EDMAC
000C 0030h EDMAC
000C 0038h EDMAC
000C 0040h EDMAC
000C 0048h EDMAC
000C 0050h EDMAC
000C 0058h EDMAC
000C 0064h EDMAC
000C 0068h EDMAC
000C 006Ch EDMAC
000C 0070h EDMAC
000C 0078h EDMAC
000C 007Ch EDMAC
000C 00C8h EDMAC
000C 00CCh EDMAC
000C 00D4h EDMAC
000C 00D8h EDMAC
PDC Control Register 0
PDC Control Register 1
PDC Status Register
PDC Pin Monitor Register
PDC Receive Data Register
Vertical Capture Register
Horizontal Capture Register
EDMAC mode register
EDMAC transmit request register
EDMAC receive request register
Transmit descriptor list start address register
Receive descriptor list start address register
ETHERC/EDMAC status register
ETHERC/EDMAC status interrupt permission register
Transmit/receive status copy enable register
Receive missed-frame counter register
Transmit FIFO threshold register
FIFO depth register
Receiving method control register
Transmit FIFO underrun counter
Receive FIFO overflow counter
Independent output signal setting register
Flow control start FIFO threshold setting register
Receive data padding insert register
Transmit interrupt setting register
Receive buffer write address register
Receive descriptor fetch address register
Transmit buffer read address register
Transmit descriptor fetch address register
PCCR0
PCCR1
PCSR
PCMONR
PCDR
VCR
HCR
EDMR
EDTRR
EDRRR
TDLAR
RDLAR
EESR
EESIPR
TRSCER
RMFCR
TFTR
FDR
RMCR
TFUCR
RFOCR
IOSR
FCFTR
RPADIR
TRIMD
RBWAR
RDFAR
TBRAR
TDFAR
Number Access
of Bits Size
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Number of Access States
Related
ICLKPCLK ICLK<PCLK Function
9 PCLKB or
more
Rounded up
to the nearest
integer
greater than 1
+ 9/
(frequency
ratio of ICLK/
PCLKB)^*6
9 PCLKB or
more
Rounded up
to the nearest
integer
greater than 1
+ 9/
(frequency
ratio of ICLK/
PCLKB)^*6
9 PCLKB or
more
Rounded up
to the nearest
integer
greater than 1
+ 9/
(frequency
ratio of ICLK/
PCLKB)^*6
9 PCLKB or
more
Rounded up
to the nearest
integer
greater than 1
+ 9/
(frequency
ratio of ICLK/
PCLKB)^*6
2, 3PCLKA
2 ICLK PDC
2, 3PCLKA
2 ICLK
2, 3PCLKA
2 ICLK
2, 3PCLKA
2 ICLK
2, 3PCLKA
2 ICLK
2, 3PCLKA
2 ICLK
2, 3PCLKA
2 ICLK
5, 6 PCLKA
—
EDMAC
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
EDMAC
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
5, 6 PCLKA
—
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 127 of 208