RX63N_15 Datasheet, PDF (165/210 Pages) Renesas Technology Corp – Renesas MCUs

RX63N Group, RX631 Group
5. Electrical Characteristics
Table 5.20 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*¹, VREFH0 = 2.7 V to AVCC0*¹,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Symbol Min.
RSPI RSPCK clock cycle
Master
Slave
t_SPcyc
2
8
RSPCK clock high
pulse width
RSPCK clock low
pulse width
RSPCK clock rise/
fall time
Master
Slave
Master
Slave
Output [packages with 177 to
144 pins]
Output [packages with 100
pins or less]
t_SPCKWH (t_SPcyc – t_SPCKR
– t_SPCKF) / 2 – 3
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2
t_SPCKWL (t_SPcyc – t_SPCKR
– t_SPCKF) / 2 – 3
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2
t_SPCKr, —
t_SPCKf
—
Input
—
Data input setup time Master
VCC  3.0 V t_SU
15
[packages
with 177 to
VCC < 3.0 V
20
144 pins]
Master [packages with 100
30
pins or less]
Data input hold time
SSL setup time
Slave
Master
Slave
Master
Slave
t_H
t_LEAD
20 – t_Pcyc
0
20 + 2 × t_Pcyc
1
4
SSL hold time
Master
Slave
t_LAG
1
4
Max.
4096
4096
—
—
—
—
5
10
1
—
—
—
—
—
—
8
—
8
—
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t_Pcyc: PCLK cycle
Unit*² Test Conditions
t_Pcyc
Figure 5.42
C = 30_PF
ns
ns
ns
μs
ns
Figure 5.43 to
Figure 5.46
C = 30_PF
ns
t_SPcyc
t_Pcyc
t_SPcyc
t_Pcyc
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 165 of 208